ESPROS Cadence Analog Reference Flow
The ESPROS-Cadence Analog Reference Flow streamlines the process of designing analog/MS chips targeted to our ESPROS Photonic CMOS™ process. The flow has been proven through silicon. By taking advantage of ESPROS process technology and Cadence Virtuoso® Custom Design Platform, designers can benefit from a design flow that reduces time-to-silicon and avoids costly re-spins.
- compatible with Cadence Virtuoso® Custom Design Platform
- predictable path to silicon
- starting point for customized design flow
- reduce development risk
ESPROS PDK is a foundry design kit is created to build a bridge between design and foundry. The process design kit includes schematic symbols, techfiles, callback functions for design parameters, parameterized cells for custom layout, schematic-driven layout automation, and provides an easy link to the DRC/LVS/LPE rule deck.
Our PDK is available for commercial use. Please contact us for further details.
Analog Reference Flow